GATE EC 2016 Set 2 — Question 27
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Digital Circuits → Sequential Logic → Ring & Johnson Counters
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Question
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor and the supply voltage is . The D flip-flops and are initialized with logic values and , respectively. The clock has a duty cycle.
The average power dissipated (in mW) in the resistor is ________
Correct answer
1.45 to 1.55
Solution
Reading the circuit. The five D flip-flops form a ring (shift-right) counter: on every clock edge and . From the figure, the OR gate is driven by (the line tapped between and ) and by , and its output drives .State sequence starting from :
The pattern then repeats, so the OR output is HIGH () for 3 of every 5 clock periods. The clock duty cycle does not matter, because the flip-flop outputs change only at clock edges and stay constant for a full period.Power. When the output is HIGH, . Averaged over the cycle:Answer: mW
| Clock period | ||
|---|---|---|
| 1 | 01010 | 0 |
| 2 | 00101 | 1 |
| 3 | 10010 | 0 |
| 4 | 01001 | 1 |
| 5 | 10100 | 1 |
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