GATE EC 2016 Set 2 — Question 27
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Digital Circuits → Sequential Logic → Ring & Johnson Counters
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Question
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor and the supply voltage is . The D flip-flops and are initialized with logic values and , respectively. The clock has a duty cycle.
The average power dissipated (in mW) in the resistor is ________
Correct answer
1.45 to 1.55
Solution
1.Identify the circuit operation: The circuit is a 5-bit ring counter. The state of the register shifts right on every clock edge, and the output of the last flip-flop () is fed back to the first ().
2.Determine the sequence of states: Given the initial state , the sequence of states over 5 clock cycles is:
- Cycle 1:
- Cycle 2:
- Cycle 3:
- Cycle 4:
- Cycle 5:
3.Determine the OR gate output: The OR gate takes inputs from and . Let's find the output for each state:
- Cycle 1:
- Cycle 2:
- Cycle 3:
- Cycle 4:
- Cycle 5:
4.Calculate power dissipation:
- Peak power when the output is high (): .
- Average power: .
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