GATE EC 2017 Set 2 — Question 43
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Digital Circuits → Sequential Logic → Sequence Detectors
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Question
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is .
If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is _______
Correct answer
4 to 4
Solution
The state diagram shows that the FSM detects the sequence '101'. Let's trace the input sequence 10101101001101 starting from state :
1.Input 1:
2.Input 0:
3.Input 1: (Out = 1, count = 1)
4.Input 0:
5.Input 1: (Out = 1, count = 2)
6.Input 1:
7.Input 0:
8.Input 1: (Out = 1, count = 3)
9.Input 0:
10.Input 0:
11.Input 1:
12.Input 1:
13.Input 0:
14.Input 1: (Out = 1, count = 4)
The total number of times 'Out' is 1 is 4.Continue learning with Success Tracker
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