GATE EC 2017 Set 2 — Question 44
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Digital Circuits → Combinational Logic → Adders & Subtractors
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Question
Figure I shows a 4-bit ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder are initially reset to 0.
At , the inputs to the 4-bit adder are changed to , and . The output of the ripple carry adder will be stable at (in ns) = ________.
Correct answer
50 to 50
Solution
1.Analyze Full Adder (FA) Delays:
- Sum . Delay from is ns. Delay from is ns.
- Carry .
- Path from to via AND-OR: ns.
- Path from to via XOR-AND-OR: ns.
- Path from to via AND-OR: ns.
- Initial state: All inputs and outputs are 0.
- New inputs: , , .
- FA0 (): becomes 1 at ns. . stays 0.
- FA1 (): . No transitions.
- FA2 (): . This transition occurs via the AND-OR path from at ns. . No transition.
- FA3 (): . This transition depends on and occurs at ns. . No transition.
The last signal to stabilize is at ns. Therefore, the output is stable at 50 ns.
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