GATE EC 2021 Set 1 — Question 41
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Digital Circuits → Combinational Logic → Critical Path Delay
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Question
The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively.
If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is
If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is
Correct answer
(C) 6 ns
Solution
Let's analyze the propagation delays for each path from input to output Y.Path 1: P to Y
- P goes to XOR gate (delay 4 ns).
- Output of XOR goes to MUX (delay 1 ns).
- Total delay = 4 ns + 1 ns = 5 ns.
- Q goes to XOR gate (delay 4 ns).
- Output of XOR goes to MUX (delay 1 ns).
- Total delay = 4 ns + 1 ns = 5 ns.
- R goes to AND gate (delay 2 ns).
- Output of AND goes to MUX (delay 1 ns).
- Total delay = 2 ns + 1 ns = 3 ns.
- S goes to AND gate (delay 2 ns).
- Output of AND goes to MUX (delay 1 ns).
- Total delay = 2 ns + 1 ns = 3 ns.
- T goes to MUX (delay 1 ns).
- Total delay = 1 ns.
- P or Q to XOR (delay 4 ns).
- XOR output to MUX select line (no additional gate delay, but this signal controls the MUX).
- The MUX itself has a delay of 1 ns from its data inputs to output. The select line delay is usually considered part of the MUX delay for data path. However, if the select line itself has a delay, it can affect which data input is selected. In this problem, the select line is driven by the XOR gate output.
- The XOR gate output (P XOR Q) drives the select line of the first MUX (delay 4 ns).
- The AND gate output (R AND S) drives the select line of the second MUX (delay 2 ns).
1.Path through the first MUX (inputs P, Q, R, S):
- Input P/Q to XOR gate: 4 ns
- Output of XOR gate (which is also for the first MUX) is available at 4 ns.
- Data inputs to the first MUX are R (from AND gate) and S (from AND gate).
- R to AND gate: 2 ns
- S to AND gate: 2 ns
- Output of AND gate (data input to MUX) is available at 2 ns.
- The first MUX itself has a delay of 1 ns.
- The output of the first MUX is available at .
- Delay to select line ( from XOR) = 4 ns.
- Delay to data input (from AND) = 2 ns.
- Output of first MUX = ns.
- The output of the first MUX is available at 5 ns.
- Input T is available at 0 ns.
- The select line for the second MUX is driven by the AND gate output (R AND S), which is available at 2 ns.
- The second MUX itself has a delay of 1 ns.
- The final output Y is available at .
- Delay to select line ( from AND) = 2 ns.
- Delay to data input (from first MUX) = 5 ns.
- Final output Y = ns.
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