GATE EC 2021 Set 1 — Question 41
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Digital Circuits → Combinational Logic → Critical Path Delay
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Question
The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively.
The select inputs of both multiplexers are driven by input T, and the output Y is taken from the second (right-hand) multiplexer.If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is
The select inputs of both multiplexers are driven by input T, and the output Y is taken from the second (right-hand) multiplexer.If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is
Correct answer
(C) 6 ns
Solution
Label the signals: (AND, 2 ns), (XOR, 4 ns), (AND, 2 ns). MUX1 selects (T=0) or (T=1). The second AND gives . MUX2 outputs (T=0) or (T=1).Because T is held constant, the delay must be found for each value of T separately. The longest topological path (XOR to MUX1 to AND to MUX2 = 8 ns) is a false path: XOR is selected only when T=0, and then MUX2 selects instead.
- T = 0: . Delay = 2 (AND) + 1 (MUX2) = 3 ns.
- T = 1: MUX1 passes , ready at ns. The AND gate needs both (2 ns) and MUX1 (3 ns), so it settles at ns. MUX2 adds 1 ns: 6 ns.
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