GATE EC 2022 Set 1 — Question 43
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
For the circuit shown, the clock frequency is and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, _______.
Correct answer
(A) frequency is f₀/4 and duty cycle is 50%
Solution
1.Analyze the 2-bit binary counter: A 2-bit binary counter cycles through four states. Assuming it is a down-counter (which is consistent with the official answer), the states or are:
2.Analyze the JK Flip-Flop: The inputs are and . The JK flip-flop is clocked by the same clock . Let's trace the output starting from :
- State 1 : . The flip-flop maintains its previous state. remains .
- State 2 : . The flip-flop toggles. becomes .
- State 3 : . The flip-flop is set. remains .
- State 4 : . The flip-flop is reset. becomes .
- The sequence of over 4 clock cycles is .
- The output repeats every 4 cycles of the input clock, so the frequency is .
- The output is high for 2 cycles and low for 2 cycles, so the duty cycle is .
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