GATE EC 2023 Set 1 — Question 63
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
In a given sequential circuit, initial states are and . For a clock frequency of , the frequency of signal in , is _ (rounded off to the nearest integer).
Correct answer
250 to 250
Solution
The circuit consists of two D flip-flops.
Let's analyze the connections:
Let's trace the states starting from initial state .
The sequence of states is:
The sequence repeats every 4 clock cycles. This is a 4-state counter.The signal sequence is:
The period of is 4 clock cycles.Clock frequency .
The period of the clock .The period of is .
The frequency of is .Rounded off to the nearest integer, the frequency of is .
Let's analyze the connections:
- The input to the first D flip-flop () is .
- The input to the second D flip-flop () is .
Let's trace the states starting from initial state .
| Clock Cycle | Next State | Next State | ||||
|---|---|---|---|---|---|---|
| Initial | 1 | 0 | 1 | 1 | ||
| 1 | 1 | 1 | 0 | 1 | 1 | 1 |
| 2 | 0 | 1 | 0 | 0 | 0 | 1 |
| 3 | 0 | 0 | 1 | 0 | 0 | 0 |
| 4 | 1 | 0 | 1 | 1 | 1 | 0 |
| 5 | 1 | 1 | 0 | 1 | 1 | 1 |
The sequence repeats every 4 clock cycles. This is a 4-state counter.The signal sequence is:
The period of is 4 clock cycles.Clock frequency .
The period of the clock .The period of is .
The frequency of is .Rounded off to the nearest integer, the frequency of is .
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