GATE EC 2023 Set 1 — Question 62
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Digital Circuits → Data Converters → Sample & Hold
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Question
A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of . The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of with 12-bit accuracy is _______ (rounded off to two decimal places).
Correct answer
8.3 to 8.34
Solution
In a sample and hold circuit, the capacitor charges through the switch resistance. The voltage across the capacitor is given by:
where is the full-scale voltage and is the time constant.For -bit accuracy, the error must be less than or equal to the quantization step size relative to full scale, which is typically defined as :
Taking the natural logarithm on both sides:
Given:
Rounding off to two decimal places, the time required is .
where is the full-scale voltage and is the time constant.For -bit accuracy, the error must be less than or equal to the quantization step size relative to full scale, which is typically defined as :
Taking the natural logarithm on both sides:
Given:
- bits
Rounding off to two decimal places, the time required is .
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