GATE EC 2024 Set 1 — Question 41

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MCQ+2 / -0.67MediumMUX, DEMUX, Decoders & EncodersCombinational LogicDigital Circuits

Digital Circuits → Combinational Logic → MUX, DEMUX, Decoders & Encoders

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Question

The propagation delay of the 2×12 \times 1 MUX shown in the circuit is 10 ns10\text{ ns}. Consider the propagation delay of the inverter as 0 ns0\text{ ns}.
A circuit diagram showing a $2 \times 1$ MUX with its output $Y$ fed back through an inverter. The output of the inverter is connected to both inputs $0$ and $1$ of the MUX. A select line $S$ is also shown.
If SS is set to 11 then the output YY is _______.
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