GATE EC 2024 Set 1 — Question 42
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
The sequence of states () of the given synchronous sequential circuit is
Correct answer
(B) 11 → 00 → 10 → 01 → 00
Solution
The circuit consists of two T flip-flops, labeled and , with clock input CLK. The inputs to the T flip-flops are and .From the circuit diagram:
Now, let's construct the state table based on these next state equations:
Based on this state table, the possible state sequences are:
(A) : Incorrect, as .
(B) : This sequence implies transitions , , , . None of these transitions match the derived state table (, , , ).
(C) : Incorrect, as .
(D) : Incorrect, as .There is a discrepancy between the state sequence derived from the given circuit diagram using standard T flip-flop operation and all the provided options. However, as per the instruction to match the provided correct answer, we select (B). If the circuit were intended to produce the sequence in option (B), the logic for the and inputs would need to be different from what is shown in the diagram.The final answer is
1.The input to the first flip-flop is connected to the output of the second flip-flop. So, .
2.The input to the second flip-flop is connected to the output of an XOR gate. The inputs to the XOR gate are and . So, .
The characteristic equation for a T flip-flop is .Using these, we can write the next state equations for the circuit:Now, let's construct the state table based on these next state equations:
| Current State () | Next State () | ||
|---|---|---|---|
| 00 | 0 | 00 | |
| 01 | 0 | 10 | |
| 10 | 1 | 11 | |
| 11 | 1 | 01 |
1.If the circuit is in state 00, it remains in state 00 (). This is a stable state.
2.If the circuit starts from any other state, it enters the cycle (a cycle of three states).
Let's compare this with the given options:(A) : Incorrect, as .
(B) : This sequence implies transitions , , , . None of these transitions match the derived state table (, , , ).
(C) : Incorrect, as .
(D) : Incorrect, as .There is a discrepancy between the state sequence derived from the given circuit diagram using standard T flip-flop operation and all the provided options. However, as per the instruction to match the provided correct answer, we select (B). If the circuit were intended to produce the sequence in option (B), the logic for the and inputs would need to be different from what is shown in the diagram.The final answer is
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