GATE EC 2024 Set 1 — Question 42
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
The sequence of states () of the given synchronous sequential circuit is
In the figure, both gates are 2-input OR gates: and . Both flip-flops are T flip-flops clocked by the common CLK.
Correct answer
(B) 11 → 00 → 10 → 01 → 00
Solution
Read the figure. Both gates are OR gates:For a T flip-flop, .State table ( next):
So the circuit cycles , and state enters this cycle at :
| 00 | 1 | 0 | 10 |
| 01 | 0 | 1 | 00 |
| 10 | 1 | 1 | 01 |
| 11 | 1 | 1 | 00 |
- (A) : goes to , not .
- (C) : goes to .
- (D) : goes to .
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