GATE EC 2025 Set 1 — Question 45
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Digital Circuits → Combinational Logic → MUX, DEMUX, Decoders & Encoders
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Question
A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input is set to logic ‘0’ and is set to logic ‘1’ at all times. The timing diagram of the inputs and are also shown below.The sequence of output from time to is ________.
Correct answer
(A) 1011
Solution
The circuit consists of two D flip-flops ( and ) and two 2-to-1 multiplexers. From the circuit diagram:
After the edge: .
Output .
After the edge: .
Output .
After the edge: .
Output .
After the edge: .
Output .Thus, the sequence of output from to is 1011.
1.The input to the first flip-flop is . Since , .
2.The input to the second flip-flop is . Since , .
3.The output is the XNOR of the two flip-flop outputs: .
We trace the state transitions at each positive clock edge () based on the timing diagram:- At : .
After the edge: .
Output .
- At : .
After the edge: .
Output .
- At : .
After the edge: .
Output .
- At : .
After the edge: .
Output .Thus, the sequence of output from to is 1011.
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