GATE EC 2026 Set 1 — Question 49
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.MCQ+2 / -0.67MediumShift RegistersSequential LogicDigital CircuitsSR, D, JK & T Flip-Flops
Digital Circuits → Sequential Logic → Shift Registers
Last updated
Question
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.Which of the following options gives the correct binary representation () of the content of the shift register immediately after the clock transition (positive edge)?
Correct answer
(A) 00011111
Solution
Initially, the shift register (SR) and D flip-flop are cleared: and .
The XOR gate input is the serial output of the shift-left register () and a logic 1. Thus, .
The serial input to the SR is the output of the D flip-flop.
Tracing the states at each positive clock edge:
The XOR gate input is the serial output of the shift-left register () and a logic 1. Thus, .
The serial input to the SR is the output of the D flip-flop.
Tracing the states at each positive clock edge:
1.Initial: . .
2.After edge: , shifts left with . .
3.After edge: , shifts left with . .
4.After edge: , shifts left with . .
5.After edge: , shifts left with . .
6.After edge: , shifts left with . .
Wait, if we consider the first edge as the first transition and the state after it, the sequence of values shifted in is . This results in . If the question implies 5 '1's are shifted in due to the delay logic, the answer is .Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE EC question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Sequential Logic
2026 Set 1 Q20In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of…2026 Set 1 Q27A binary ripple counter is designed to count to . Which of the following…2026 Set 1 Q35The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a…2026 Set 1 Q42The address of the first location of a 256 kilo byte (KB) memory is . Choose the correct…2026 Set 1 Q45What is the complement of ?