GATE EC 2026 Set 1 — Question 49
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Digital Circuits → Sequential Logic → Shift Registers
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Question
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.Which of the following options gives the correct binary representation () of the content of the shift register immediately after the clock transition (positive edge)?
Correct answer
(A) 00011111
Solution
Read the figure: the shift register shifts left, so its serial output is and its serial input enters at . The D flip-flop takes . The XOR gate combines with logic 1, so the serial input isThe register and the flip-flop share the same clock. On each positive edge:
stays 0 for the first five edges, so stays 0 and a 1 is shifted in on every edge.
- the register shifts left and loads into ;
- the flip-flop loads .
| Edge | serial in | Register | new |
|---|---|---|---|
| 1 | 1 | 00000001 | 0 |
| 2 | 1 | 00000011 | 0 |
| 3 | 1 | 00000111 | 0 |
| 4 | 1 | 00001111 | 0 |
| 5 | 1 | 00011111 | 0 |
- (B) 10111111 and (C) 00111111 would need more ones shifted in than five edges allow.
- (D) 11000011 does not follow from the shifting pattern.
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