GATE CS 2023 Set 1 — Question 42
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Computer Organization & Architecture → Combinational Circuits → Encoders & Decoders
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Question
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.
The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?
Correct answer
(C) (0, 8, 16, 24)
Solution
1.Address Mapping: The total address space is 12 bits (IA11 to IA0). IA4 and IA3 are used for block selection via the decoder. The other 10 bits (IA11-IA5 and IA2-IA0) are used as the internal address (
Addr) for each 1 KB block.2.Starting Locations: For the starting location of any block, the internal address must be 0. This means .
3.Block Selection:
- X1 is selected when . Full address: .
- X2 is selected when . Full address: .
- X3 is selected when . Full address: .
- X4 is selected when . Full address: .
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