GATE CS 2026 Set 2 — Question 18

MCQ+1 / -0.33MediumInterrupt-Driven I/OI/O OrganizationComputer Organization & Architecture

Computer Organization & Architecture → I/O Organization → Interrupt-Driven I/O

Last updated 5 September 2026

Question

Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism. S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt. Which one of the following options is correct with respect to S1 and S2 ?

Correct answer (C) S1 is true and S2 is false Solution Statement S1 is TRUE . In a non-vectored interrupt mechanism, the CPU jumps to a fixed memory location (the general ISR) upon receiving an interrupt. This ISR must then poll the devices to determine which one caused the interrupt, which consumes time. In contrast, a vectored interrupt mechanism provides the address of the specific ISR directly, allowing the CPU to jump immediately to the correct handler, which is faster. Statement S2 is FALSE . Daisy-chaining is a hardware mechanism for priority resolution and device identification. The interrupt acknowledge signal propagates through the devices in series. The requesting device closest to the CPU intercepts the signal and places its vector on the bus. The CPU does not poll the devices individually; the hardware propagation handles the selection. Turn this into a strength. Explore AI-powered practice and doubt support with Success Tracker.

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Correct answer (C) S1 is true and S2 is false Solution Statement S1 is TRUE . In a non-vectored interrupt mechanism, the CPU jumps to a fixed memory location (the general ISR) upon receiving an interrupt. This ISR must then poll the devices to determine which one caused the interrupt, which consumes time. In contrast, a vectored interrupt mechanism provides the address of the specific ISR directly, allowing the CPU to jump immediately to the correct handler, which is faster. Statement S2 is FALSE . Daisy-chaining is a hardware mechanism for priority resolution and device identification. The interrupt acknowledge signal propagates through the devices in series. The requesting device closest to the CPU intercepts the signal and places its vector on the bus. The CPU does not poll the devices individually; the hardware propagation handles the selection.

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