GATE CS 2026 Set 1 — Question 16
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Computer Organization & Architecture → Instruction Pipelining → Data Hazards (RAW, WAR, WAW)
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Question
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
Correct answer
(B) Read-after-write
Solution
In a standard pipelined processor (like the classic 5-stage MIPS pipeline), instructions are executed in overlapping stages. A Read-after-Write (RAW) dependency occurs when an instruction tries to read a register before a previous instruction has written to it. Since the read stage (ID) occurs before the write-back stage (WB), would read an old value unless forwarding or stalling is used. This is a true data dependency and constitutes a data hazard.
- Read-after-read (RAR): Not a hazard; multiple instructions can read the same register simultaneously.
- Write-after-read (WAR): An anti-dependency. In simple in-order pipelines, reads happen early (ID) and writes happen late (WB), so the read completes before the write, avoiding a hazard.
- Write-after-write (WAW): An output dependency. In simple in-order pipelines, writes happen in order in the WB stage, avoiding a hazard.
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