GATE CS 2026 Set 1 — Question 16
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.MCQ+1 / -0.33EasyData Hazards (RAW, WAR, WAW)Instruction PipeliningComputer Organization & Architecture
Computer Organization & Architecture → Instruction Pipelining → Data Hazards (RAW, WAR, WAW)
Last updated
Question
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
Correct answer
(B) Read-after-write
Solution
A data hazard arises when overlapping execution lets an instruction see (or leave behind) the wrong value of a register operand. Consider instruction followed by in program order:
- Read-after-write (RAW), a true dependency: reads a register that writes. In a pipeline, reads its operands (ID/EX) before has written its result back (WB), so without forwarding or stalling would read the stale value. This is the data hazard every pipelined processor must handle, including the classic in-order 5-stage pipeline.
- Read-after-read (RAR): both instructions only read the register; no value changes, so there is never a hazard.
- Write-after-read (WAR), an anti-dependency: in an in-order pipeline, reads happen early and writes happen late, so always reads before writes and no hazard occurs.
- Write-after-write (WAW), an output dependency: in an in-order pipeline, writes are retired in program order in WB, so no hazard occurs.
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE CS question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Instruction Pipelining
2026 Set 1 Q14Match each addressing mode in List I with a data element or an element of a data structure (in…2026 Set 1 Q15Consider a processor P whose instruction set architecture is the load-store architecture. The…2026 Set 2 Q18Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In…2026 Set 1 Q38The size of the physical address space of a processor is bytes. The capacity of a cache…2026 Set 2 Q44Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format…