60 solved GATE CS questions on Computer Organization & Architecture, drawn from 7 exam years and grouped by year. Every question shows the official answer and a step-by-step solution.
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Identify the instruction format, datapath stages, and memory hierarchy parameters before computing execution time or hit rates. These selected foundations connect instruction sets, pipelining, caches, and I/O without replacing a full architecture course.
Our study notes and original examples support the PYQs below; they are not official exam questions or a replacement for the current syllabus.
Each instruction goes through fetch, decode, execute, memory access, and writeback stages. The cycle time of a single-cycle processor equals the slowest instruction's total delay. A multi-cycle design lets different instructions take different numbers of cycles.
Check yourself: Which stages does the current instruction actually use?
Pipelining overlaps stages of consecutive instructions. Data hazards occur when an instruction needs a result not yet written back. Forwarding can resolve some hazards without stalling. Control hazards from branches may require flushing, prediction, or delayed branching. Pipeline speedup approaches the number of stages only for long instruction streams.
Check yourself: Does forwarding resolve this hazard, or is a stall still required?
A cache with 2^s sets and associativity A holds A × 2^s blocks. An address splits into tag, set index, and block offset fields. A direct-mapped cache (A = 1) has no placement choice within a set; fully associative has one set. Conflict misses occur only when A < total blocks.
Check yourself: How many bits are in the offset, index, and tag fields?
Average memory access time = hit time + miss rate × miss penalty. Compulsory misses occur on the first access to a block. Capacity misses occur when the working set exceeds cache size. Increasing associativity reduces conflict misses but may increase hit time.
Check yourself: Are you using the local miss rate or the global miss rate for multi-level caches?
Virtual memory translates virtual addresses to physical frames through page tables. TLBs cache recent translations. Page faults service from disk, so their penalty is orders of magnitude larger than a cache miss. I/O can be memory-mapped or port-based; DMA transfers data without CPU intervention per word.
Check yourself: Is the page in physical memory, or does this access cause a page fault?
Original teaching example · not a PYQ
Original mini-example: a direct-mapped cache has 64 blocks, each 16 bytes. Byte addresses are 16 bits. Find the number of tag, index, and offset bits.
6 tag bits, 6 index bits, 4 offset bits.
A processor has a cache hit time of 2 ns, miss rate of 10%, and miss penalty of 50 ns. What is the average memory access time?
7 ns.
AMAT = 2 + 0.10 × 50 = 2 + 5 = 7 ns. The hit time applies to every access; the miss penalty applies only to the 10% that miss.
Supplemental reading, not an official GATE reading list or an endorsement of these notes.
Free supplemental course materials covering processor design, pipelining, caches, and virtual memory with lecture notes and exercises.
This page shows 60 recent questions from the released archive, newest first. For older questions and complete papers, browse all GATE CS papers. Questions can carry more than one subject tag; counts are not marks weightage.
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