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GATE CS Computer Organization & Architecture Previous Year Questions

12 solved GATE CS questions on Computer Organization & Architecture, drawn from 1 exam year and grouped by year. Every question shows the official answer and a step-by-step solution.

GATE CS 202412 questions

  1. Set 1 Q15Which one of the following statements is FALSE?MCQ · +1 marks · Easy
  2. Set 1 Q30Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB)…MSQ · +1 marks · Medium
  3. Set 1 Q53Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of…MSQ · +2 marks · Medium
  4. Set 1 Q54Consider a 512 GB hard disk with 32 storage surfaces. There are 4096 sectors per track and each sector holds 1024 bytes of data. The number of cylinders in the…NAT · +2 marks · Medium
  5. Set 1 Q55The baseline execution time of a program on a 2 GHz single core machine is 100 nanoseconds (ns). The code corresponding to 90% of the execution time can be…NAT · +2 marks · Medium
  6. Set 1 Q56A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss…NAT · +2 marks · Medium
  7. Set 2 Q11Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular…MCQ · +1 marks · Medium
  8. Set 2 Q31An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of…MSQ · +1 marks · Easy
  9. Set 2 Q53Consider a disk with the following specifications: rotation speed of 6000 RPM, average seek time of 5 milliseconds, 500 sectors/track, 512-byte sectors. A file…NAT · +2 marks · Hard
  10. Set 2 Q57A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field,…NAT · +2 marks · Medium
  11. Set 2 Q58A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then…NAT · +2 marks · Medium
  12. Set 2 Q61A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The…NAT · +2 marks · Medium

Other GATE CS topics

Engineering Mathematics(23)General Aptitude(20)Programming & Data Structures(17)Databases(12)Computer Networks(12)Operating System(10)Compiler Design(9)Theory of Computation(8)Digital Logic(8)Algorithms(5)

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