GATE CS 2026 Set 1 — Question 38
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Computer Organization & Architecture → Memory Hierarchy & Cache → Cache Numericals
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Question
The size of the physical address space of a processor is bytes. The capacity of a cache memory unit is bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a -way set-associative cache, where and . Let the length of the TAG field be bits for the direct mapped cache, and bits for the set-associative cache.Which one of the following options is true?
Correct answer
(A) N = M + L
Solution
Given:
Number of lines (blocks) in cache = .
For Direct Mapped, Number of Sets = Number of Lines = .
Index bits = bits.
Tag bits () = PA - Index - Block Offset
bits.Case 2: -way Set-Associative Cache
.
Number of sets = .
Index bits = bits.
Tag bits () = PA - Index - Block Offset
Relationship between and
Since and , substituting into the equation for gives:
Thus, option (A) is correct.
- Physical address space size = bytes Physical Address (PA) = 32 bits.
- Cache capacity = bytes.
- Block size = 128 bytes = bytes Block Offset = 7 bits.
Number of lines (blocks) in cache = .
For Direct Mapped, Number of Sets = Number of Lines = .
Index bits = bits.
Tag bits () = PA - Index - Block Offset
bits.Case 2: -way Set-Associative Cache
.
Number of sets = .
Index bits = bits.
Tag bits () = PA - Index - Block Offset
Relationship between and
Since and , substituting into the equation for gives:
Thus, option (A) is correct.
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