GATE CS 2026 Set 1 — Question 54
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Computer Organization & Architecture → Memory Hierarchy & Cache → TLB & EAT
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Question
Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.For a given memory reference, which of the following sequences of events can NEVER happen?
Correct answer
(B) TLB hit, Page table miss, Cache hit; (C) TLB miss, Page table miss, Cache hit
Solution
In a system with a physically addressed cache and a TLB, we analyze the sequences based on the given assumptions:
1.A TLB hit implies that the virtual-to-physical address translation is found in the TLB. This mapping can only exist if the page is currently resident in main memory (i.e., a Page table hit). Therefore, a TLB hit always implies a Page table hit.
2.The problem states: "when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid." This means if a page is not in main memory (a Page table miss), then any data belonging to that page cannot be found in the cache in a valid state (i.e., a Cache miss is guaranteed for that data).
Let's evaluate each sequence:- A. TLB miss, Page table hit, Cache hit:
- Possible. The virtual-to-physical mapping is not in the TLB (TLB miss), but the page is found in main memory (Page table hit). Since the page is in main memory, its data can be in the cache (Cache hit). This is a common scenario for the first access to a page after a context switch or TLB flush, where the page is already in main memory and its data is in the cache.
- B. TLB hit, Page table miss, Cache hit:
- NEVER happens. A TLB hit implies that the page is in main memory (Page table hit). This directly contradicts the "Page table miss" event in the sequence. Therefore, this sequence is impossible.
- C. TLB miss, Page table miss, Cache hit:
- NEVER happens. A "Page table miss" means the page is not in main memory. According to the problem's assumption, if a page is not in main memory, its corresponding blocks in the cache are marked as invalid. Therefore, a "Cache hit" for data from a page that is not in main memory is impossible.
- D. TLB miss, Page table miss, Cache miss:
- Possible. The virtual-to-physical mapping is not in the TLB (TLB miss). The page is not in main memory (Page table miss), leading to a page fault. Consistent with the page not being in main memory, the data is also not found in the cache (Cache miss). This is a standard scenario for accessing a page that is not currently resident in main memory.
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