GATE EC 2015 Set 3 — Question 24
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ( input). The counter corresponding to this circuit is
Correct answer
(A) a modulo-5 binary up counter
Solution
1.Counter Type: The flip-flops are negative-edge triggered (indicated by the bubble on the clock input). The output of each stage is connected to the clock input of the next stage. This configuration forms a ripple up counter.
2.Reset Logic: The NAND gate provides an active-low reset signal to the inputs. The inputs to the NAND gate are and . The reset occurs when and .
3.Counting Sequence:
- Resets to immediately.
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