GATE EC 2015 Set 3 — Question 25

Let the inputs be $E_1, E_2, E_3$ and the output be $V_o$. The inputs are either 0V (logic 0) or 10V (logic 1).Case 1: Any input is LOW (0V).
Let's assume $E_1 = 0V$. The anode of diode $D_1$ is at 0V. The output $V_o$ is the voltage at the common cathode point. If any of the diodes is forward biased, it will conduct. Since the diodes are ideal, a forward-biased diode acts as a short circuit. The anode of $D_1$ is at 0V. The cathode is at $V_o$. For $D_1$ to be forward biased, $V_o$ must be less than 0V, but the circuit structure prevents this. However, the resistor is connected to +10V. If $V_o$ were to be high, say 10V, then $D_1$ would be strongly forward biased (Anode at 0V, Cathode at 10V). Current would flow from the 10V supply, through the resistor, and through the diode $D_1$ to the 0V input. Since the diode is ideal, it will clamp the voltage $V_o$ to the lowest input voltage. Therefore, if any input is 0V, the corresponding diode will conduct and pull the output $V_o$ to 0V (logic 0).Case 2: All inputs are HIGH (10V).
Let $E_1 = E_2 = E_3 = 10V$. The anodes of all three diodes are at 10V. The output $V_o$ is connected to the +10V supply through the resistor. Since the anodes are at 10V, for any diode to conduct, its cathode voltage ($V_o$) must be less than 10V. If we assume no load is connected to $V_o$, no current flows through the resistor. Therefore, there is no voltage drop across the resistor, and $V_o$ will be equal to the supply voltage, which is 10V. In this state, the voltage across each diode is $V_{anode} - V_{cathode} = 10V - 10V = 0V$. The diodes are not conducting (or are at the edge of conduction). The output $V_o$ is 10V (logic 1).Summary (Truth Table):

• If any input is 0, the output is 0.
• Only when all inputs are 1, the output is 1.

This behavior corresponds to the truth table of a 3-input AND gate.Therefore, the circuit represents a 3-input AND gate.