GATE EC 2015 Set 3 — Question 56

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MCQ+2 / -0.67MediumShift RegistersSequential LogicDigital Circuits

Digital Circuits → Sequential Logic → Shift Registers

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Question

A three bit pseudo random number generator is shown. Initially the value of output Y=Y2Y1Y0Y = Y_2 Y_1 Y_0 is set to 111. The value of output YY after three clock cycles is
three bit pseudo random number generator circuit diagram
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