GATE EC 2016 Set 3 — Question 54
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.NAT+2 / -0MediumCombinational LogicDigital CircuitsMUX, DEMUX, Decoders & Encoders
Digital Circuits → Combinational Logic → MUX, DEMUX, Decoders & Encoders
Last updated
Question
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are , and , respectively. If all the inputs and are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is __________
Correct answer
6 to 6
Solution
To find the maximum propagation delay, we analyze the paths from the inputs to the output based on the state of the select signal .
1.Multiplexer Logic:
- MUX1 select input .
- MUX2 select input (due to the inverter).
- MUX1 selects input '1', which is .
- MUX2 select is , so it selects input '0', which is .
- The critical path is: .
- Total delay = .
- MUX1 selects input '0', which is .
- MUX2 select is , so it selects input '1', which is the output of MUX1.
- The critical path is: .
- Total delay = .
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE EC question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Combinational Logic
2026 Set 1 Q20In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of…2026 Set 1 Q27A binary ripple counter is designed to count to . Which of the following…2026 Set 1 Q35The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a…2026 Set 1 Q42The address of the first location of a 256 kilo byte (KB) memory is . Choose the correct…2026 Set 1 Q45What is the complement of ?