GATE EC 2016 Set 3 — Question 55
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
For the circuit shown in the figure, the delay of the bubbled NAND gate is and that of the counter is assumed to be zero.
If the clock (Clk) frequency is , then the counter behaves as a
Correct answer
(D) mod-8 counter
Solution
1.Clock Period: The clock frequency is , so the clock period .
2.Gate Logic: The "bubbled NAND" gate shown has bubbles on its inputs. According to De Morgan's law, a NAND gate with inverted inputs is equivalent to an OR gate: .
3.Reset Condition: The output of this gate is connected to the active-low RESET pin. The counter resets when the gate output is , which occurs only when (state 0).
4.Timing Analysis: The gate has a propagation delay of , which is twice the clock period (). In a synchronous counter, for a reset to truncate the sequence, the reset signal must be generated and applied within the same clock cycle or be synchronized.
5.Conclusion: Since the reset condition only occurs at the initial state (000) and the logic delay () exceeds the clock period (), the reset signal does not effectively truncate the natural states of the 3-bit counter. Therefore, the counter cycles through all 8 states (0 to 7) and behaves as a mod-8 counter.
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