GATE EC 2018 Set 1 — Question 56
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Digital Circuits → Probability → Expectation & Variance
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Question
In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data using clock . The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of , where the parameters and are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.
If the probability of input data bit () transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node , is _______.
Correct answer
0.82 to 0.86
Solution
In the given circuit, the XOR gate output is . The D Flip-Flop samples at the rising edge of the clock . From the timing diagram, the input data transitions after the rising edge of . When a transition occurs in , the sampled value remains at the previous state until the next rising edge. Thus, and will have different logic levels from the time of transition () until the next rising edge (). The duration of this interval is .During this interval, the XOR output is logic HIGH (3.3 V). If no transition occurs, and are identical, and is logic LOW (0 V).The average voltage is given by:
Given :
.
Given :
.
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