GATE EC 2019 Set 1 — Question 23

When the width of the pMOS transistor ($W_p$) is increased, its transconductance parameter $\beta_p = \mu_p C_{ox} (W_p/L_p)$ increases. This makes the pMOS transistor stronger.For a CMOS inverter, the switching threshold voltage ($V_M$) is given by:$$V_M = \frac{V_{Tn} + \sqrt{\frac{\beta_p}{\beta_n}}(V_{DD} - |V_{Tp}|)}{1 + \sqrt{\frac{\beta_p}{\beta_n}}}$$
where $V_{Tn}$ is the nMOS threshold voltage and $V_{Tp}$ is the pMOS threshold voltage.If $\beta_p$ increases, the ratio $\sqrt{\frac{\beta_p}{\beta_n}}$ increases. This will cause $V_M$ to shift towards $V_{DD}$.Noise Margins are defined as:
NM$_L$ (Low Noise Margin) = $V_{IL} - V_{OL}$
NM$_H$ (High Noise Margin) = $V_{OH} - V_{IH}$For an ideal CMOS inverter, $V_{OL} = 0$ and $V_{OH} = V_{DD}$.
$V_{IL}$ is the input voltage at which the slope of the transfer characteristic is -1 in the low-to-high transition region.
$V_{IH}$ is the input voltage at which the slope of the transfer characteristic is -1 in the high-to-low transition region.When the pMOS becomes stronger (larger $\beta_p$), the inverter's switching point ($V_M$) shifts towards $V_{DD}$. This means the output will transition from high to low at a higher input voltage. Consequently, $V_{IH}$ will increase, and $V_{IL}$ will decrease.Since $V_{OH}$ and $V_{OL}$ remain $V_{DD}$ and $0$ respectively (assuming ideal output swings):
NM$_L = V_{IL} - V_{OL} = V_{IL} - 0 = V_{IL}$. If $V_{IL}$ decreases, NM$_L$ decreases.
NM$_H = V_{OH} - V_{IH} = V_{DD} - V_{IH}$. If $V_{IH}$ increases, NM$_H$ decreases.However, the question asks about the effect on noise margins. Let's re-evaluate the effect of $V_M$ shift.If $V_M$ shifts towards $V_{DD}$, it means the inverter is more easily pulled down by the nMOS for a given input, or it takes a higher input to pull the output low. This makes the inverter more sensitive to low input voltages and less sensitive to high input voltages.More precisely, increasing $W_p$ (and thus $\beta_p$) makes the pMOS stronger relative to the nMOS. This shifts the VTC (Voltage Transfer Characteristic) to the right (i.e., $V_M$ increases). A higher $V_M$ means the inverter switches at a higher input voltage.When $V_M$ increases:
$V_{IL}$ (the point where the slope is -1 on the rising edge of the VTC) will decrease.
$V_{IH}$ (the point where the slope is -1 on the falling edge of the VTC) will increase.NM$_L = V_{IL} - V_{OL}$. Since $V_{OL}$ is typically 0V, NM$_L = V_{IL}$. If $V_{IL}$ decreases, NM$_L$ decreases.
NM$_H = V_{OH} - V_{IH}$. Since $V_{OH}$ is typically $V_{DD}$, NM$_H = V_{DD} - V_{IH}$. If $V_{IH}$ increases, NM$_H$ decreases.This implies both NM$_L$ and NM$_H$ decrease. This contradicts option B.Let's reconsider the definition of equal rise and fall times. Equal rise and fall times imply $\beta_n = \beta_p$ (or $\mu_n W_n = \mu_p W_p$ for equal $L$). If $W_p$ is increased, then $\beta_p$ becomes greater than $\beta_n$. This makes the pMOS stronger than the nMOS.When pMOS is stronger, the VTC shifts to the right (higher $V_M$).For a CMOS inverter, the noise margins are:
NM$_L = V_{IL} - V_{OL}$
NM$_H = V_{OH} - V_{IH}$If the VTC shifts to the right (higher $V_M$):

• The output will stay high for a wider range of low input voltages, meaning $V_{IL}$ decreases. Thus, NM$_L$ decreases.
• The output will transition to low at a higher input voltage, meaning $V_{IH}$ increases. Thus, NM$_H$ decreases.

This result (both decrease) is not among the options. Let's check common interpretations or specific conditions.In some contexts, $V_{IL}$ and $V_{IH}$ are defined relative to $V_M$. If $V_M$ shifts, the symmetry of the noise margins changes.Let's re-examine the effect of a stronger pMOS on the VTC and noise margins. A stronger pMOS means the pull-up is stronger. This shifts the switching threshold $V_M$ towards $V_{DD}$.If $V_M$ increases (shifts right):

• The region where the output is high ($V_{OH}$) extends to higher input voltages. This means $V_{IL}$ (the point where the output starts to drop significantly from $V_{OH}$) will increase. So, NM$_L$ increases.
• The region where the output is low ($V_{OL}$) starts at a higher input voltage. This means $V_{IH}$ (the point where the output has dropped significantly to $V_{OL}$) will also increase. So, NM$_H$ decreases (since $V_{DD} - V_{IH}$).

Let's verify this with a typical VTC. If the VTC shifts right, the point where the slope is -1 on the left side ($V_{IL}$) moves right (increases). The point where the slope is -1 on the right side ($V_{IH}$) also moves right (increases).So, if $V_{IL}$ increases, NM$_L$ increases.
If $V_{IH}$ increases, NM$_H$ decreases.This matches option (B).Final check:

• Increasing $W_p$ makes pMOS stronger.
• Stronger pMOS shifts $V_M$ towards $V_{DD}$ (i.e., $V_M$ increases).
• A higher $V_M$ means the inverter is more robust against low input noise (it takes a higher input to make the output drop from $V_{OH}$). So, $V_{IL}$ increases, leading to an increase in NM$_L$.
• A higher $V_M$ also means the inverter is less robust against high input noise (it switches to low at a higher input, but the $V_{IH}$ point also shifts right, reducing the margin from $V_{DD}$). So, $V_{IH}$ increases, leading to a decrease in NM$_H$.

Therefore, NM$_L$ increases and NM$_H$ decreases.The final answer is $\boxed{B}$