GATE EC 2019 Set 1 — Question 35
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Digital Circuits → Sequential Logic → Ripple & Synchronous Counters
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Question
In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is . The frequency of the signal at is ______ .
Correct answer
4 to 4
Solution
The given circuit is a synchronous sequential circuit. Let the states of the flip-flops be .
From the circuit diagram, the input equations are:
(The AND gate inputs are connected to the inverted outputs of both flip-flops)
Let's trace the state transitions starting from an initial state :
This is a modulo-3 counter. The output frequency at any flip-flop output ( or ) is the clock frequency divided by the modulus of the counter.
From the circuit diagram, the input equations are:
(The AND gate inputs are connected to the inverted outputs of both flip-flops)
Let's trace the state transitions starting from an initial state :
1.Initial state:
, . Next state: 2.Current state:
, . Next state: 3.Current state:
, . Next state: The sequence of states is This is a modulo-3 counter. The output frequency at any flip-flop output ( or ) is the clock frequency divided by the modulus of the counter.
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