GATE EC 2019 Set 1 — Question 49

MCQ+2 / -0.67MediumFSM (Mealy & Moore)Sequential LogicDigital Circuits

Digital Circuits → Sequential Logic → FSM (Mealy & Moore)

Last updated 5 September 2026

Question

Sequential circuit consisting of a D flip-flop, a NAND gate, and a 2-to-1 Multiplexer. The MUX select line is $A$. MUX input '1' is connected to $Q$, and input '0' is connected to $\bar{Q}$. The NAND gate inputs are $Q$ and the MUX output $Y$. The NAND output is connected to the $D$ input of the flip-flop.

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