GATE EC 2019 Set 1 — Question 63

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NAT+2 / -0MediumCMOS VTC & Noise MarginCombinational LogicDigital Circuits

Digital Circuits → Combinational Logic → CMOS VTC & Noise Margin

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Question

A CMOS inverter, designed to have a mid-point voltage VIV_I equal to half of VddV_{dd}, as shown in the figure, has the following parameters:Vdd=3 VV_{dd} = 3\text{ V}
μnCox=100 μA/V2\mu_n C_{ox} = 100\text{ }\mu\text{A/V}^2; Vtn=0.7 VV_{tn} = 0.7\text{ V} for nMOS
μpCox=40 μA/V2\mu_p C_{ox} = 40\text{ }\mu\text{A/V}^2; Vtp=0.9 V|V_{tp}| = 0.9\text{ V} for pMOS
The ratio of (WL)n(\frac{W}{L})_n to (WL)p(\frac{W}{L})_p is equal to ______ (rounded off to 3 decimal places).
CMOS inverter circuit and its voltage transfer characteristic (VTC) curve
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