60 solved GATE EC questions on Network Theory, drawn from 11 exam years and grouped by year. Every question shows the official answer and a step-by-step solution.
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These selected foundations connect circuit theorems, transient and AC analysis, and two-port descriptions. Distinguish DC equilibrium, switching transients, and sinusoidal steady state. The original ideal-element problems are symbolic educational exercises, not electrical construction instructions.
Our study notes and original examples support the PYQs below; they are not official exam questions or a replacement for the current syllabus.
Choose a reference node. Resistor current from a toward b is (Va − Vb)/R. Kirchhoff's current law sums signed currents to zero. For the passive sign convention, reference current enters the positive voltage terminal; positive vi then means absorbed power.
Check yourself: Does a negative current simply reverse your chosen arrow?
For a linear resistive one-port, Vth is the open-circuit terminal voltage. Find Rth with independent voltage sources shorted and independent current sources opened. Retain dependent sources and use a test source when needed. Superpose voltages or currents, not powers, because power is generally quadratic.
Check yourself: Is the load excluded, and did each source receive the correct zero-value replacement?
At finite DC equilibrium, ideal capacitors are open and inductors short. These substitutions fail during switching. Without impulsive excitation, capacitor voltage and inductor current are continuous. A first-order RC response uses initial and final values and τ = Rseen C.
Check yourself: Have you found the post-switch resistance seen by the capacitor?
Phasors describe single-frequency sinusoidal steady state, excluding startup. Use ZL = jωL and ZC = 1/(jωC), with ω = 2πf in rad/s and f in Hz. Sinusoidal RMS equals peak/√2. With RMS phasors, average power is Re(VI*), where I* conjugates I.
Check yourself: Are both voltage and current phasors RMS, at the same frequency?
With both port currents entering the network, z parameters satisfy V1 = z11 I1 + z12 I2 and V2 = z21 I1 + z22 I2. Setting I2 = 0 specifies an open output port, not a short.
Check yourself: Which port variable must vanish for your parameter measurement?
Original teaching example · not a PYQ
Original mini-example: an ideal DC source fixes node s at +12 V relative to reference b. A 3 kΩ resistor joins s to a; a 6 kΩ resistor joins a to b. Find the equivalent at a–b and the current through an added 2 kΩ load from a to b.
Vth = 8 V, Rth = 2 kΩ, load current = 2 mA, and load voltage = 4 V.
Separately, an ideal 1 μF capacitor initially at 6 V discharges through only 2 kΩ from t = 0, without impulsive excitation. What is its voltage at t = 2 ln(3) ms?
2 V with the original voltage polarity.
The final voltage is zero and τ = 2 ms. Hence v(t) = 6 exp(−t/τ) = 6/3 = 2 V. Use the transient response, not a phasor.
Supplemental reading, not an official GATE reading list or an endorsement of these notes.
Free supplemental notes: revisit lecture 3 for network equivalents, 12 for first-order systems, and 16–17 for sinusoidal steady state and impedance.
This page shows 60 recent questions from the released archive, newest first. For older questions and complete papers, browse all GATE EC papers. Questions can carry more than one subject tag; counts are not marks weightage.
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