GATE CS 2014 Set 1 — Question 53
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stalls
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Question
Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is ______________________.
Correct answer
4 to 4
Solution
Number of stages in the pipeline, .For a non-pipelined processor, the execution time per instruction is the sum of the delays of all stages. Since stages are perfectly balanced:For the pipelined processor, the ideal CPI (Cycles Per Instruction) is 1. However, there are stalls.
Percentage of instructions with stalls = 25%.
Stall cycles per such instruction = 2.Average stall cycles per instruction:The actual CPI for the pipelined processor:The execution time per instruction in the pipeline:The speedup is the ratio of non-pipelined execution time to pipelined execution time:The speedup achieved is 4.
Percentage of instructions with stalls = 25%.
Stall cycles per such instruction = 2.Average stall cycles per instruction:The actual CPI for the pipelined processor:The execution time per instruction in the pipeline:The speedup is the ratio of non-pipelined execution time to pipelined execution time:The speedup achieved is 4.
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