GATE CS 2014 Set 2 — Question 65
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Computer Organization & Architecture → Memory Hierarchy & Cache → Memory Interleaving
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Question
Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________
Correct answer
10000 to 10000
Solution
To find the maximum number of stores that can be initiated, we need to determine the bottleneck of the system: either the bus speed or the memory module availability.Given:
The bus is occupied for 100 ns for every store. Since only one request can be on the bus at a time, the minimum time between initiating two consecutive stores is 100 ns.
Max stores limited by bus = .2. Memory Limit:
Each memory module is busy for 600 ns. With 8 modules, we can ideally start a new operation on a different module every ns without conflict (assuming sequential access to different modules).
Since the bus limit (100 ns) is slower than the memory limit (75 ns), the bus is the bottleneck.Verification of Interleaving:
- Bus occupation time per request () = 100 ns.
- Memory module cycle time () = 100 ns (bus) + 500 ns (internal) = 600 ns.
- Number of memory modules () = 8.
- Total time available () = 1 ms = ns.
The bus is occupied for 100 ns for every store. Since only one request can be on the bus at a time, the minimum time between initiating two consecutive stores is 100 ns.
Max stores limited by bus = .2. Memory Limit:
Each memory module is busy for 600 ns. With 8 modules, we can ideally start a new operation on a different module every ns without conflict (assuming sequential access to different modules).
Since the bus limit (100 ns) is slower than the memory limit (75 ns), the bus is the bottleneck.Verification of Interleaving:
- Store 1 initiates at on Module 1. Bus free at 100. Module 1 free at 600.
- Store 2 initiates at on Module 2. Bus free at 200. Module 2 free at 700.
- ...
- Store 8 initiates at on Module 8. Bus free at 800. Module 8 free at 1300.
- Store 9 initiates at . We need a free module. Module 1 became free at 600, so it is available.
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