GATE CS 2015 Set 1 — Question 55

NAT+2 / -0MediumSpeedup & EfficiencyInstruction PipeliningComputer Organization & Architecture

Computer Organization & Architecture → Instruction Pipelining → Speedup & Efficiency

Last updated 5 September 2026

Question

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is_________.

R_1 = 2.5 \text{ GHz}

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R_1 = 2.5 \text{ GHz}

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