GATE CS 2015 Set 2 — Question 53

NAT+2 / -0MediumData ForwardingInstruction PipeliningComputer Organization & ArchitecturePipeline StallsPipeline Stages & Throughput

Computer Organization & Architecture → Instruction Pipelining → Data Forwarding

Last updated 5 September 2026

Question

Consider the sequence of machine instructions given below: MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4 In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is___________.

Correct answer 13 to 13 Solution Stages: IF, OF, WB take 1 cycle each; PO takes 3 cycles for MUL, 5 for DIV and 1 for ADD/SUB. There is a single PO unit, and results are forwarded from the end of PO directly to the next instruction that needs them. Dependencies: ADD needs R5 (from MUL) and R6 (from DIV); SUB needs R7 (from ADD). Instruction IF OF PO WB MUL R5, R0, R1 12 3-5 6 DIV R6, R2, R3 23 6-10 11 ADD R7, R5, R6 3 4 (stalls) 1112 SUB R8, R7, R4 4 5 (stalls) 1213 DIV cannot start PO until MUL leaves the PO stage, so its PO occupies cycles 6-10. ADD needs R6, which is forwarded at the end of cycle 10, so ADD's PO is in cycle 11 and WB in 12. SUB needs R7, forwarded at the end of cycle 11, so SUB's PO is in cycle 12 and WB in 13. The last instruction completes write-back in cycle 13. Answer: 13 Turn this into a strength. Explore AI-powered practice and doubt support with Success Tracker.

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Correct answer 13 to 13 Solution Stages: IF, OF, WB take 1 cycle each; PO takes 3 cycles for MUL, 5 for DIV and 1 for ADD/SUB. There is a single PO unit, and results are forwarded from the end of PO directly to the next instruction that needs them. Dependencies: ADD needs R5 (from MUL) and R6 (from DIV); SUB needs R7 (from ADD). Instruction IF OF PO WB MUL R5, R0, R1 12 3-5 6 DIV R6, R2, R3 23 6-10 11 ADD R7, R5, R6 3 4 (stalls) 1112 SUB R8, R7, R4 4 5 (stalls) 1213 DIV cannot start PO until MUL leaves the PO stage, so its PO occupies cycles 6-10. ADD needs R6, which is forwarded at the end of cycle 10, so ADD's PO is in cycle 11 and WB in 12. SUB needs R7, forwarded at the end of cycle 11, so SUB's PO is in cycle 12 and WB in 13. The last instruction completes write-back in cycle 13. Answer: 13

Instruction	IF	OF	PO	WB
MUL R5, R0, R1	1	2	3-5	6
DIV R6, R2, R3	2	3	6-10	11
ADD R7, R5, R6	3	4 (stalls)	11	12
SUB R8, R7, R4	4	5 (stalls)	12	13

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