GATE CS 2015 Set 3 — Question 34
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Computer Organization & Architecture → Memory Hierarchy & Cache → Direct-Mapped Cache
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Question
Consider a machine with a byte addressable main memory of bytes, block size of 16 bytes and a direct mapped cache having cache lines. Let the addresses of two consecutive bytes in main memory be and . What are the tag and cache line address (in hex) for main memory address ?
Correct answer
(A) E, 201
Solution
Main memory size = bytes Physical Address = 20 bits.
Block size = 16 bytes = bytes Block Offset = 4 bits.
Number of cache lines = Line Number (Index) = 12 bits.
Tag bits = Physical Address bits - (Line Number bits + Block Offset bits)
Tag bits = bits.Address given:
Binary representation (20 bits): Splitting the address:
Block size = 16 bytes = bytes Block Offset = 4 bits.
Number of cache lines = Line Number (Index) = 12 bits.
Tag bits = Physical Address bits - (Line Number bits + Block Offset bits)
Tag bits = bits.Address given:
Binary representation (20 bits): Splitting the address:
- Block Offset (LSB 4 bits): (F)
- Line Number (Next 12 bits):
- Tag (MSB 4 bits):
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