GATE CS 2016 Set 2 — Question 43
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.NAT+2 / -0MediumPipeline Stages & ThroughputInstruction PipeliningComputer Organization & Architecture
Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput
Last updated
Question
Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies , , and such that . If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ________ GHz, ignoring delays in the pipeline registers.
Correct answer
3.9 to 4.1
Solution
1.Determine current stage latencies:
- Current frequency = 3 GHz.
- Cycle time ns.
- In a pipeline, the cycle time is determined by the longest stage latency. Thus, ns.
- Given relations: and .
- Express all in terms of :
- Since is the largest multiple of , is the longest stage.
- Therefore, ns.
- ns.
- ns.
- The longest stage ( ns) is split into two equal stages.
- New latencies for these split stages: ns.
- The new stages have latencies: ns, ns, ns, ns.
- New max latency ns (since ).
- New Frequency = GHz.
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE CS question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Instruction Pipelining
2026 Set 1 Q14Match each addressing mode in List I with a data element or an element of a data structure (in…2026 Set 1 Q15Consider a processor P whose instruction set architecture is the load-store architecture. The…2026 Set 1 Q16Which one of the following dependencies among the register operands of different instructions can…2026 Set 2 Q18Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In…2026 Set 1 Q38The size of the physical address space of a processor is bytes. The capacity of a cache…