GATE CS 2017 Set 1 — Question 25
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Computer Organization & Architecture → Memory Hierarchy & Cache → Cache Numericals
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Question
Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ________.
Correct answer
0.05 to 0.05
Solution
Let the number of instructions be .
Total memory accesses = .L1 Cache:
Miss rate of L1 () = 0.1
Number of L1 misses = Total accesses .L2 Cache:
The misses from L1 are the accesses to L2.
Number of L2 accesses = Number of L1 misses = .Number of L2 misses is given as 7 per 1000 instructions.
Number of L2 misses = .L2 Miss Rate ():The miss rate of L2 is 0.05.
Total memory accesses = .L1 Cache:
Miss rate of L1 () = 0.1
Number of L1 misses = Total accesses .L2 Cache:
The misses from L1 are the accesses to L2.
Number of L2 accesses = Number of L1 misses = .Number of L2 misses is given as 7 per 1000 instructions.
Number of L2 misses = .L2 Miss Rate ():The miss rate of L2 is 0.05.
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