GATE CS 2017 Set 2 — Question 53
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.NAT+2 / -0EasyDirect-Mapped CacheMemory Hierarchy & CacheComputer Organization & Architecture
Computer Organization & Architecture → Memory Hierarchy & Cache → Direct-Mapped Cache
Last updated
Question
Consider a machine with a byte addressable main memory of bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is ________.
Correct answer
18 to 18
Solution
Main memory size = bytes Address bits = 32.
Block size = 32 bytes = bytes Block offset = 5 bits.
Number of cache lines = 512 = Index bits = 9 bits.
In a direct mapped cache, the physical address is divided as follows:
Total address bits = bits.
Block size = 32 bytes = bytes Block offset = 5 bits.
Number of cache lines = 512 = Index bits = 9 bits.
In a direct mapped cache, the physical address is divided as follows:
| Tag | Index | Block Offset |
|---|---|---|
| bits | 9 bits | 5 bits |
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE CS question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Memory Hierarchy & Cache
2026 Set 1 Q14Match each addressing mode in List I with a data element or an element of a data structure (in…2026 Set 1 Q15Consider a processor P whose instruction set architecture is the load-store architecture. The…2026 Set 1 Q16Which one of the following dependencies among the register operands of different instructions can…2026 Set 2 Q18Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In…2026 Set 1 Q38The size of the physical address space of a processor is bytes. The capacity of a cache…