GATE CS 2018 Set 1 — Question 15

MCQ+1 / -0.33EasyRISC vs CISCInstructions & Addressing ModesComputer Organization & Architecture

Computer Organization & Architecture → Instructions & Addressing Modes → RISC vs CISC

Last updated 5 September 2026

Question

Consider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?

Correct answer (D) I, II and III Solution RISC (Reduced Instruction Set Computer) processors are designed with several key characteristics to improve performance: 1. Register-to-register operations : Most instructions operate on registers, with separate Load and Store instructions for memory access. This simplifies the instruction set and allows for faster execution. 2. Fixed-length instruction format : All instructions are of the same size (e.g., 32 bits), which makes decoding much faster and easier to pipeline. 3. Hardwired control unit : Unlike CISC processors that often use microprogrammed control units, RISC processors use hardwired logic to execute instructions in a single clock cycle whenever possible. Therefore, all three characteristics (I, II, and III) are typical of RISC designs. Turn this into a strength. Explore AI-powered practice and doubt support with Success Tracker.

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Correct answer (D) I, II and III Solution RISC (Reduced Instruction Set Computer) processors are designed with several key characteristics to improve performance: 1. Register-to-register operations : Most instructions operate on registers, with separate Load and Store instructions for memory access. This simplifies the instruction set and allows for faster execution. 2. Fixed-length instruction format : All instructions are of the same size (e.g., 32 bits), which makes decoding much faster and easier to pipeline. 3. Hardwired control unit : Unlike CISC processors that often use microprogrammed control units, RISC processors use hardwired logic to execute instructions in a single clock cycle whenever possible. Therefore, all three characteristics (I, II, and III) are typical of RISC designs.

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