GATE CS 2018 Set 1 — Question 44

Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.
MCQ+2 / -0.67MediumSet-Associative CacheMemory Hierarchy & CacheComputer Organization & ArchitectureCache Numericals

Computer Organization & Architecture → Memory Hierarchy & Cache → Cache Numericals

Last updated

Question

The size of the physical address space of a processor is 2P2^P bytes. The word length is 2W2^W bytes. The capacity of cache memory is 2N2^N bytes. The size of each cache block is 2M2^M words. For a KK-way set-associative cache memory, the length (in number of bits) of the tag field is
Your answer

Choose one option, then check your answer.

The solution stays hidden until you check.

Continue learning with Success Tracker

A step still unclear? Work through it with support

Use Success Tracker to ask about the reasoning, then try another GATE CS question to check your understanding.

AI-powered practice· Unlimited practice on eligible plans
PYQs with solutions
Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
Practice that adapts
Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
AI doubt support
Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.

Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.

This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.

More questions on Memory Hierarchy & Cache