GATE CS 2018 Set 1 — Question 60
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput
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Question
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.The number of clock cycles required for completion of execution of the sequence of instructions is ______.
Correct answer
219 to 219
Solution
In a pipeline with no hazards, the total time is determined by the time it takes for the first instruction to reach the bottleneck stage, the total time spent by all instructions in that bottleneck stage, and the time for the last instruction to exit the remaining stages.
Total Cycles = .
1.Pipeline Stages: IF (1), ID (1), OF (1), PO (variable), WB (1).
2.Bottleneck Stage: PO is the bottleneck as it takes cycle.
3.Cycles to reach PO: The first instruction takes 3 cycles (IF, ID, OF) to reach the PO stage.
4.Total cycles in PO: Sum of cycles for all 100 instructions in the PO stage:
- 40 instructions 3 cycles = 120 cycles
- 35 instructions 2 cycles = 70 cycles
- 25 instructions 1 cycle = 25 cycles
- Total PO cycles = cycles.
Total Cycles = .
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