GATE CS 2019 Set 1 — Question 12
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Computer Organization & Architecture → Memory Hierarchy & Cache → Memory Technologies (SRAM, DRAM, ROM)
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Question
The chip select logic for a certain DRAM chip in a memory system design is shown below.
Assume that the memory system has 16 address lines denoted by to . What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
Assume that the memory system has 16 address lines denoted by to . What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
Correct answer
(A) C800 to CFFF
Solution
The Chip Select (CS) signal is generated by a logic gate (AND gate) taking inputs from address lines through . For the chip to be enabled, CS must be active (High/1).Based on the diagram:
Prefix:
Full 16-bit address: Lower Bound (Min Address):
Set all to 0:
Hex: C800Upper Bound (Max Address):
Set all to 1:
Hex: CFFFThe range is C800 to CFFF.
- is connected directly must be 1.
- is connected directly must be 1.
- has a bubble (inverter) must be 0.
- has a bubble (inverter) must be 0.
- is connected directly must be 1.
Prefix:
Full 16-bit address: Lower Bound (Min Address):
Set all to 0:
Hex: C800Upper Bound (Max Address):
Set all to 1:
Hex: CFFFThe range is C800 to CFFF.
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