GATE CS 2019 Set 1 — Question 55
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Computer Organization & Architecture → Memory Hierarchy & Cache → Cache Numericals
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Question
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ________ bytes/sec.
Correct answer
160 to 160
Solution
1.Calculate the total data transferred per block:
Block size = 8 words 4 bytes/word = 32 bytes.2.Calculate the total time (cycles) to transfer one block:
- Time to accept address: 1 cycle
- Time to fetch data: 3 cycles
- Time to transmit data: 8 words 1 cycle/word = 8 cycles
3.Calculate the bandwidth:
Bandwidth = Bandwidth = Given clock frequency = 60 MHz = cycles/sec. Bandwidth in bytes/sec =
bytes/sec.The answer is 160.
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