GATE CS 2020 Set 1 — Question 31
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.NAT+1 / -0MediumDirect-Mapped CacheMemory Hierarchy & CacheComputer Organization & ArchitectureCache Numericals
Computer Organization & Architecture → Memory Hierarchy & Cache → Cache Numericals
Last updated
Question
A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is ________.
Correct answer
13.3 to 13.3
Solution
1.Identify Parameters:
- Hit Rate () = 0.94
- Miss Rate () =
- Cache Access Time () = 3 ns
- Block Size = 256 bytes
- Word Size = 64 bits = 8 bytes
- Number of words per block = words.
- Time to transfer first word = 20 ns.
- Time to transfer remaining 31 words = ns.
- Total Miss Penalty (time to fetch block) = ns.
- Formula:
- ns.
Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE CS question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Memory Hierarchy & Cache
2026 Set 1 Q14Match each addressing mode in List I with a data element or an element of a data structure (in…2026 Set 1 Q15Consider a processor P whose instruction set architecture is the load-store architecture. The…2026 Set 1 Q16Which one of the following dependencies among the register operands of different instructions can…2026 Set 2 Q18Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In…2026 Set 1 Q38The size of the physical address space of a processor is bytes. The capacity of a cache…