GATE CS 2020 Set 1 — Question 53
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stalls
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Question
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _______.
Correct answer
2.15 to 2.18
Solution
1.Non-pipelined Processor:
- Frequency = 2.5 GHz
- Cycle time () =
- CPI () = 5
- Execution time per instruction () =
- Frequency = 2 GHz
- Cycle time () =
- Ideal CPI = 1 (for a 5-stage pipeline)
- Stalls:
- Memory Instructions (30%): 5% cause 50 stall cycles.
- Penalty = cycles
- Branch Instructions (Rest = ): 50% cause 2 stall cycles.
- Penalty = cycles
- ALU Instructions (60%): No stalls.
- Total CPI () = Ideal CPI + Stalls =
- Execution time per instruction () =
- Speedup =
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