GATE CS 2022 Set 1 — Question 54
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Computer Organization & Architecture → Memory Hierarchy & Cache → Cache Numericals
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Question
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS…). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?
Correct answer
(A) Every access to S is a hit.; (B) Once P is brought to the cache it is never evicted.; (D) Every access to R evicts Q from the cache.
Solution
Cache parameters: Size = 2KB = 2048 bytes, Block = 64 bytes. Number of lines = . Index bits = . Offset bits = .Address mapping (Binary):
P: 0xA248 = 1010 0010 0100 1000. Index (bits 6-10): 01001 (9). Tag: 10100 (20).
Q: 0xC28A = 1100 0010 1000 1010. Index: 01010 (10). Tag: 11000 (24).
R: 0xCA8A = 1100 1010 1000 1010. Index: 01010 (10). Tag: 11001 (25).
S: 0xA262 = 1010 0010 0110 0010. Index: 01001 (9). Tag: 10100 (20).Analysis:
(A) S is always a hit because P loads the block and nothing evicts Set 9. TRUE.
(B) P is in Set 9. Only S accesses Set 9, and it's in the same block. Never evicted. TRUE.
(C) At the end, Set 9 has Block(P,S) and Set 10 has Block(R). P, S, and R reside in cache. Statement "Only R and S" implies P is not there, which is false. FALSE.
(D) Every access to R occurs after Q, finding Block(Q) in Set 10. R must evict Q. TRUE.
P: 0xA248 = 1010 0010 0100 1000. Index (bits 6-10): 01001 (9). Tag: 10100 (20).
Q: 0xC28A = 1100 0010 1000 1010. Index: 01010 (10). Tag: 11000 (24).
R: 0xCA8A = 1100 1010 1000 1010. Index: 01010 (10). Tag: 11001 (25).
S: 0xA262 = 1010 0010 0110 0010. Index: 01001 (9). Tag: 10100 (20).Analysis:
1.P and S map to Set 9 with the same Tag (20). They are in the same 64-byte block (0xA240 to 0xA27F). Accessing P brings the block containing S. No conflict between P and S.
2.Q and R map to Set 10 with different Tags (24 vs 25). They conflict.
Sequence P, Q, R, S:- P: Miss (Cold). Loads Block(P,S) into Set 9.
- Q: Miss (Cold). Loads Block(Q) into Set 10.
- R: Miss (Conflict). Evicts Q, loads Block(R) into Set 10.
- S: Hit (Block(P,S) is in Set 9).
(A) S is always a hit because P loads the block and nothing evicts Set 9. TRUE.
(B) P is in Set 9. Only S accesses Set 9, and it's in the same block. Never evicted. TRUE.
(C) At the end, Set 9 has Block(P,S) and Set 10 has Block(R). P, S, and R reside in cache. Statement "Only R and S" implies P is not there, which is false. FALSE.
(D) Every access to R occurs after Q, finding Block(Q) in Set 10. R must evict Q. TRUE.
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