GATE CS 2022 Set 1 — Question 61
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Computer Organization & Architecture → Instruction Pipelining → Branch Prediction
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Question
A processor operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for and . If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by over in executing is____________.
Correct answer
1.42 to 1.45
Solution
To find the speedup of processor over , we need to calculate the effective CPI (Cycles Per Instruction) for both processors. The speedup is the ratio of the execution time of to . Since the clock frequency and instruction count are the same for both, the speedup is the ratio of their CPIs.Step 1: Calculate CPI for
- Base CPI = 1
- Branch frequency = 30% = 0.3
- Stall penalty per branch = 2 cycles
- Pipeline stalls per instruction = cycles
- Effective
- Base CPI = 1
- Branch frequency = 0.3
- Prediction accuracy = 80% = 0.8
- Misprediction rate =
- Stalls occur only on mispredictions (wrong predictions). The penalty is the same as (2 cycles).
- Stalls per branch = cycles
- Pipeline stalls per instruction = cycles
- Effective
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