GATE CS 2023 Set 1 — Question 33

NAT+1 / -0EasyPipeline Stages & ThroughputInstruction PipeliningComputer Organization & Architecture

Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput

Last updated 5 September 2026

Question

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle. The total execution time for executing 100 instructions on this processor is________ns.

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