GATE CS 2024 Set 2 — Question 11

MCQ+1 / -0.33MediumDMA (Operation & Types)I/O OrganizationComputer Organization & Architecture

Computer Organization & Architecture → I/O Organization → DMA (Operation & Types)

Last updated 20 August 2026

Question

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

4 \text{ MHz} = 4 \times 10^6 \text{ cycles/second}

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4 \text{ MHz} = 4 \times 10^6 \text{ cycles/second}

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