GATE CS 2024 Set 2 — Question 11

MCQ+1 / -0.33MediumDMA (Operation & Types)I/O OrganizationComputer Organization & Architecture

Computer Organization & Architecture → I/O Organization → DMA (Operation & Types)

Last updated 20 August 2026

Question

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

2,56,000

3,200

25,60,000

32,000

Correct answer

Solution

1.Processor Speed:

4 \text{ MHz} = 4 \times 10^6 \text{ cycles/second}

2.DMA Usage: 1% of processor cycles.

DMA cycles per second =

0.01 \times 4 \times 10^6 = 40,000 \text{ cycles/second}

3.Data per Cycle: 8 bytes.

4.Transfer Rate (Bytes):

40,000 \text{ cycles/sec} \times 8 \text{ bytes/cycle} = 320,000 \text{ bytes/second}

5.Transfer Rate (Bits):

320,000 \text{ bytes/sec} \times 8 \text{ bits/byte} = 2,560,000 \text{ bits/second}

Result: 25,60,000 bits/sec.

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