GATE CS 2024 Set 2 — Question 31
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Computer Organization & Architecture → Instruction Pipelining → Data Hazards (RAW, WAR, WAW)
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Question
An instruction format has the following structure:Instruction Number: Opcode destination reg, source reg-1, source reg-2Consider the following sequence of instructions to be executed in a pipelined processor:I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8Which of the following statements is/are TRUE?
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8Which of the following statements is/are TRUE?
Correct answer
(A) There is a RAW dependency on R3 between I1 and I2
Solution
Let's analyze the dependencies based on the instruction format: Opcode dest, src1, src2.Instructions:
- I1:
DIV R3, R1, R2Writes , Reads - I2:
SUB R5, R3, R4Writes , Reads - I3:
ADD R3, R5, R6Writes , Reads - I4:
MUL R7, R3, R8Writes , Reads
- I1 writes .
- I2 reads .
- Since I2 follows I1 and reads the value written by I1, this is a RAW (Read-After-Write) dependency.
- This statement is TRUE.
- I1 writes .
- I3 writes .
- This is a WAW (Write-After-Write) dependency (Output dependency), not WAR.
- This statement is FALSE.
- I2 reads .
- I3 writes .
- This is a WAR (Write-After-Read) dependency (Anti-dependency), not RAW.
- This statement is FALSE.
- I3 writes .
- I4 reads .
- This is a RAW (Read-After-Write) dependency, not WAW.
- This statement is FALSE.
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