GATE CS 2024 Set 2 — Question 58
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Computer Organization & Architecture → Instruction Pipelining → Control Hazards
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Question
A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________
Correct answer
2.9 to 3.1
Solution
Given:
- Non-pipelined processor frequency .
- Non-pipelined CPI () = 6 cycles.
- Pipelined processor frequency .
- Ideal pipelined CPI = 1.
- Stalls:
- 20% of instructions cause 2 stall cycles.
- 20% of instructions cause 3 stall cycles.
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