GATE CS 2024 Set 2 — Question 58

NAT+2 / -0MediumSpeedup & EfficiencyInstruction PipeliningComputer Organization & ArchitectureData Hazards (RAW, WAR, WAW)Pipeline StallsControl Hazards

Computer Organization & Architecture → Instruction Pipelining → Control Hazards

Last updated 20 August 2026

Question

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________

Correct answer

2.9 to 3.1

Solution

Given:

Non-pipelined processor frequency $f = 2 \text{ GHz}$ .
Non-pipelined CPI ( $CPI_{np}$ ) = 6 cycles.
Pipelined processor frequency $f = 2 \text{ GHz}$ .
Ideal pipelined CPI = 1.
Stalls:
20% of instructions cause 2 stall cycles.
20% of instructions cause 3 stall cycles.

Step 1: Calculate Execution Time for Non-Pipelined Processor

T_{np} = CPI_{np} \times \text{Cycle Time} = 6 \times \frac{1}{f}

Step 2: Calculate Effective CPI for Pipelined Processor

CPI_{pipe} = \text{Ideal CPI} + \text{Average Stall Cycles per Instruction}

Average Stall Cycles:

= (0.20 \times 2) + (0.20 \times 3) + (0.60 \times 0)

= 0.4 + 0.6 + 0 = 1.0 \text{ cycles}

CPI_{pipe} = 1 + 1.0 = 2.0

Step 3: Calculate Execution Time for Pipelined Processor

T_{pipe} = CPI_{pipe} \times \text{Cycle Time} = 2.0 \times \frac{1}{f}

Step 4: Calculate Speedup

\text{Speedup} = \frac{T_{np}}{T_{pipe}} = \frac{6 \times (1/f)}{2.0 \times (1/f)} = \frac{6}{2} = 3

The speedup is 3.0.

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