GATE CS 2024 Set 2 — Question 57

NAT+2 / -0MediumInstruction FormatsInstructions & Addressing ModesComputer Organization & Architecture

Computer Organization & Architecture → Instructions & Addressing Modes → Instruction Formats

Last updated 20 August 2026

Question

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is _________

Correct answer

32 to 32

Solution

Given:

Instruction size = 32 bits
Number of registers = 16. Bits required per register = $\lceil \log_2 16 \rceil = 4$ bits.
Two register operand fields. Total bits = $2 \times 4 = 8$ bits.
Scalar field size = 16 bits.
Number of addressing modes = 8. Bits required = $\lceil \log_2 8 ceil = 3$ bits.

Let

n

be the number of bits for the opcode field.
The sum of the lengths of all fields must equal the total instruction size:

n + \text{Addressing Mode bits} + \text{Register bits} + \text{Scalar bits} = 32

n + 3 + 8 + 16 = 32

n + 27 = 32

n = 5 \text{ bits}

The maximum number of unique opcodes possible is

2^n = 2^5 = 32

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